In recent years, with finer geometries of MOS transistors and increased chip area in the semiconductor integrated circuit device, delay variation caused by variation in characteristics of the MOS transistors within a chip has increased, and this becomes a factor in tightening a timing constraint condition. In order to reduce this delay variation, a technology has been developed in which the core region of the semiconductor integrated circuit device is divided into a plurality of CMOS circuit module regions, and substrate biases of the MOS transistors are controlled for each of the CMOS circuit module regions, thereby reducing variations in the characteristics of the MOS transistors among the CMOS circuit module regions and among chips.
When variation in channel lengths of the MOS transistors within each of the CMOS circuit modules is great, a problem may arise that the variation in the characteristics within the CMOS circuit module region caused by dependency of a substrate bias effect on a channel length increases. For this reason, a technology for reducing the variation in the channel lengths of the MOS transistors within each of the CMOS circuit modules is desired.
Now, using drawings, a description will be directed to a conventional semiconductor integrated circuit device in which the core region is divided into the CMOS circuit module regions and the substrate biases of the MOS transistors in each of the CMOS circuit module regions is controlled. FIG. 6 is a plan view schematically showing an example of a configuration of the conventional semiconductor integrated circuit device. FIG. 7 is a block diagram schematically showing an example of a configuration of the CMOS circuit module region in the conventional semiconductor integrated circuit device.
A semiconductor integrated circuit device 1 includes a core region 10, and an input/output region 11 (refer to FIG. 6). The core region 10 is the region including a plurality of CMOS circuit module regions CCM11 to CCM22. The input/output region 11 is the region for inputting or outputting data.
Each of the CMOS circuit module regions CCM11 to CCM22 constitutes a rectangular shape with an X axis direction used as a longitudinal direction thereof and with a Y axis direction used as a short side direction thereof, as seen from the direction of a normal to a plane (or the direction perpendicular to the drawing; a Z axis direction). Referring to FIG. 6, the CMOS circuit module regions CCM11 to CCM22 are aligned in six columns and two rows in the core region 10. In each of the CMOS circuit module regions CCM11 to CCM22, an N well or a P well (not shown) is formed within the region, and the CMOS circuit module regions CCM11 to CCM22 are electrically separated by field oxide films (not shown) at boundaries thereof. The longitudinal direction (X axis direction) of each of the CMOS circuit module regions CCM11 to CCM22 is orthogonal to a scan direction (direction of scanning by a step-and-scan type projection exposure apparatus: Y axis direction).
In the CMOS circuit module region CCM11, a circuit functional module CFM11, a performance measurement circuit PMC11, a storage (memory) table circuit MTC11, a clock frequency control circuit CFC11, a supply voltage control circuit SVC11, and a substrate bias control circuit BBC11 are formed (refer to FIG. 7). Formation of the CMOS circuit module regions CCM12 to CCM22 is also performed in the same way as the CMOS circuit module region CCM11.
To the circuit functional module CFM11, a clock signal clk11, a supply voltage vdd11, a PMOS transistor substrate bias vbp11, an NMOS transistor substrate bias vbn11, and a measurement command signal mescmd11 are input. The circuit functional module CFM11 outputs a measurement result signal mesres11. The performance measurement circuit PMC11 outputs the measurement command signal mescmd11 and a measurement command signal mescmd12. A measurement result signal mesres11 is input to the performance measurement circuit PMC11, and the performance measurement circuit PMC11 outputs a result associated with the measurement result signal mesres11 as a performance data signal pfdat11. The measurement command signal mescmd12 and the performance data signal pfdat11 are input to the storage table circuit MTC11. The storage table circuit MTC11 outputs operation control signals opcnt11, opcnt12, and opcnt13. The clock frequency control circuit CFC11 inputs the operation control signal opcnt11 and outputs the clock signal clk11. To the supply voltage control circuit SVC11, the operation control signal opcnt12 is input. The supply voltage control circuit SVC11 outputs the supply voltage vdd11. The operation control signal opcnt13 is input to the substrate bias control circuit BBC11. The substrate bias control circuit BBC11 outputs the PMOS transistor substrate bias vbp11 and the NMOS transistor substrate bias vbn11.
Performance such as a data processing speed (or an operation speed) or power consumption of the circuit functional module CFM11 changes according to a frequency of the clock signal clk11, a voltage of the supply voltage vdd11, and voltages of the substrate biases vbp11 and vbn11 supplied to the circuit functional module CFM11. In order to maximize a ratio of the operation speed of the circuit functional module CFM11 to the power consumption of the circuit functional module CFM11 and to implement optimal control over the clock signal clk11, supply voltage vdd11, and substrate biases vbp11 and vbn11, performance measurement is performed on all combinations of the frequency of the clock signal clk11, voltage of the supply voltage vdd11, and voltages of the substrate biases vbp11 and vbn11 that can be generated by the clock frequency control circuit CFC11, supply voltage control circuit SVC11, and substrate bias control circuit BBC11, respectively, and an optimal condition is then determined.
Conventionally, when gate poly mask exposure (exposure of a mask pattern for gate formation onto a wafer substrate) using the step-and-scan type projection exposure apparatus was performed in a manufacturing process of the semiconductor integrated circuit device described above, no particular consideration was given to the scan direction therefor. Scanning was performed in the Y-axis direction in FIG. 6, for example.    [Patent Document 1]            Japanese Patent Kokai Publication No. JP-P2001-156261A            [Patent Document 2]            Japanese Patent Kokai Publication No. JP-P2004-165649A            [Patent Document 3]            Japanese Patent Kokai Publication No. JP-P2004-228417A        